Peer Review: Layout Design and Simulation Analog Neural Network Circuit Using Cmos Technology 0.35 Micron

Kurniawan, Robby and Heruseto, Brahmantyo and Prasetyo, Eri and Affandi, Hamzah (2016) Peer Review: Layout Design and Simulation Analog Neural Network Circuit Using Cmos Technology 0.35 Micron. Peer Review. (Unpublished)

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Item Type: Other
Subjects: L Education > L Education (General)
T Technology > T Technology (General)
T Technology > TA Engineering (General). Civil engineering (General)
Divisions: Fakultas Teknologi Industri > Program Studi Teknik Elektro
Depositing User: Mr Reza Chandra
Date Deposited: 16 Jun 2016 04:55
Last Modified: 16 Jun 2016 04:55
URI: http://repository.gunadarma.ac.id/id/eprint/1731

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