Design low power 135mW pipeline ADC with speed 80 MSPS 8-bit

Heruseto, Brahmantyo Design low power 135mW pipeline ADC with speed 80 MSPS 8-bit. Proceeding 2010.

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Abstract

Abstract- This paper describes a pipeline analog-todigital converter is implemented for high speed camera. In the pipeline ADC design, prime factor is designing operational amplifier with high gain so ADC have been high speed. The other advantage of pipeline is simple on concept, easy to implement in layout and have flexibility to increase speed. We made design and simulation using Mentor Graphics Software with O.351lm CMOS technology with a total power dissipation of 135 mW. Circuit techniques used include a precise comparator with latch, operational amplifier and Non-Overlapping clock. A switched capacitor is used to sample, multiplying and hold at each stage. Simulation a worst caseDNL and 1NL of 0,6 LSB. The design operates at 3,3 Vde. The speed camera cmos at 10.000 frames/so

Item Type: Article
Uncontrolled Keywords: Design; low power; pipeline
Subjects: A General Works > AI Indexes (General)
Depositing User: Mr Reza Chandra
Date Deposited: 28 Feb 2014 04:19
Last Modified: 28 Feb 2014 04:19
URI: http://repository.gunadarma.ac.id/id/eprint/712

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