Desain Komparator Presisi untukAplikasiADC Pipeline 1-bit/stage Menggunakan CMOS Teknologi AMS 0,35 Mm

Afandi, Harnzah and Ch, Erma Triawati Desain Komparator Presisi untukAplikasiADC Pipeline 1-bit/stage Menggunakan CMOS Teknologi AMS 0,35 Mm. Seminar Nasional dan ExpoTeknik Elektro 2011. ISSN 2088-9984

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Abstract

Pipeline ADC I-bit/stage requires a careful ADC sub and hove a high accuracy, the appropriate is a precision comparator thol has Vos approximately equal to Ov. In precision comparator, there are three important parts that must be duigTled that block pre-amp, decision blocks, and block buffer.. In this design method used is based on manual calculations required specifications. From the results simulated with CAD mentor graphics technology with the size 0/ AMS (Awtria Micro Systems) 0.35 um CMOS. then the simulation results in the anoiysis if there is a difference with both theories be revised manually count and circuit simulation. Block design pre-amp fimction to change the voltage level to current level.Desain decision block is the heart of the comparator which comert Ihe current into a voltage by adding a slider hysteresis to minimize noise levels that occur. Design block buffer is a differential voltage level converter circuit into a binary logic (0 and I), by applying its own refraction and adding a buffer not to increase the strengthening and-isolaling tM capacitive load 10 the refraction of hii own. The results are the strengthening of the comparator A'll :::: 5 10 minimize the offset error with ISS =-30jJA to get logether at a voltage mock::: 1.65 V.

Item Type: Article
Uncontrolled Keywords: comparator precision; pre-amp; decision; buffer
Subjects: A General Works > AI Indexes (General)
Divisions: Fakultas Teknologi Industri > Program Studi Teknik Elektro
Depositing User: Mr Reza Chandra
Date Deposited: 28 Feb 2014 07:13
Last Modified: 28 Feb 2014 07:13
URI: http://repository.gunadarma.ac.id/id/eprint/933

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