Desain Pembangkit Pulsa Clock Non-OverIapping untuk Aplikasi ADC Pipeline 1-bit/stage menggunakan CmOS Teknologi AMS 0,35 Mm

Afandi, Hamzah and Pertiwi, Atit Desain Pembangkit Pulsa Clock Non-OverIapping untuk Aplikasi ADC Pipeline 1-bit/stage menggunakan CmOS Teknologi AMS 0,35 Mm. Seminar Nasional dan ExpoTeknik Elektro 2011. ISSN 2088-9984

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Abstract

In this paper discussed about the pulse generator is very impartant to the process of converting analog to digital. In the sampling phase and multiplying the ADC requires a clock pulse to a mode that does not intersect

Item Type: Article
Uncontrolled Keywords: sampling; multiplying; pulse generators
Subjects: A General Works > AI Indexes (General)
Divisions: Fakultas Teknologi Industri > Program Studi Teknik Elektro
Depositing User: Mr Reza Chandra
Date Deposited: 28 Feb 2014 07:20
Last Modified: 28 Feb 2014 07:20
URI: http://repository.gunadarma.ac.id/id/eprint/943

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