Designa ndS imulationR eversibleT SG GateF or Application of Efficient Adder Circuits

Abstract

In the recenty -earsr, cv-ersiblelo gic has emergeda s a promising technologt having its applications in low power CMOS, quantum compirting narrctechnolog| and opical computing. ThJchssical it otgal su"t L aNo, OR, and ExoR arc not reversible. This paper proposes a new 4 * 4 reversible gate called 'TSG- g"t.. Ii" proposed gate is used to design efficibnt {lerunits. The most significant aspect of the proposed gate is that it can work singly as a revirsible full adder i.e reversible full adder Tl nol be implemented with a singte gate onty. The proposcd gate is tlen used to design reversible frpple carry and carry skip adden. It is demonstratedth at the adder architechuesd esigred using the proposed late are much *tter and opimized, cornpared to th ir existilS counterparB in literature; in terms olnumber of ret"oiUI" gies and garbage outputs. Result of sinulated circuit shown in this paper. Thug this p4er provides the initial thre*rold to-building o]*oi. complex system which can execut more complicated operations using reversiblelogic.