Hardware Implementation of Fast Detection Anti-collision Algorithm For RFID System

Abstract

This paper presents a proposed hardware implementation of Fast Detection Anti-collision Algorithm ((FDACA) for Radio Frequency Identification (RFID) system. Our proposed FDACA is base on the deterministic anti-collision technique. Novelty of the proposed FDACA is fast identification by reducing the number of iterations during the identification process. In this technique, powered tags were divided into group of four for every Read cycle. Meanwhile, the proposed FDACA also reads the identification (ID) bits at once regardless of its length. Furthermore the proposed FDACA does not require the tags to remember the instructions from the reader during the communication process in which the tags were treated as address carrying devices only. As a result simple, small, low cost and memoryless tags can be produced. The proposed FDACA system was designed using Verilog HDL. The system was simulated using Modelsim XE II and synthesized using Xilinx synthesis technology (XST). The system has been successfully implemented in hardware using Field Programmable Grid Array (FPGA) board model Virtex II Xc2v250. Finally the output waveforms from the FPGA have been displayed on the Tektronix Logic Analyzer model TLA 5201 for real time verification. The results show that the proposed FDACA can identify tags without error until 100MHz and more.